1. Field of the Invention
Embodiments of the present invention generally relate to using redundant circuitry on integrated circuits in order to increase manufacturing yields and connect internal, functional circuit blocks with a predetermined set of interfaces.
2. Description of the Related Art
Integrated circuits are manufactured on wafers, which are typically made of silicon that undergoes several processing steps. Once wafer processing is complete, the integrated circuits on the wafer are tested. This testing procedure is known as wafer sort. After wafer sort, the integrated circuits (or the “die”) are separated from one another, and the good die, those that pass wafer sort testing, are packaged. The packaged parts are retested in a procedure referred to as final test. The packaged parts that pass final test may then be used or sold.
It is desirable to have as many good die per wafer as possible. This helps amortize the expense of a wafer among a greater number of die, thus reducing per die costs. Unfortunately, in a conventional integrated circuit, one defective or nonfunctional circuit block out of many is enough to render an entire die inoperable.
This is particularly troublesome for large integrated circuits. The number of errors in processing, such as opens, shorts, crystal defects, metal bridging, and other problems, tend to increase exponentially proportional to die area. Thus, larger integrated circuits are more likely to have a defect than a smaller circuit. Also, since there are fewer die per wafer to start with, this higher rate of attrition has a particularly negative effect.
Therefore, it is desirable to include some number of redundant circuit blocks on an integrated circuit. If one circuit block is defective, the integrated circuit functionality can be retained if the redundant circuit block can be substituted for the defective block. But saving the functionality of an integrated circuit does not make economic sense if the overhead or cost in terms of die area of the redundant circuitry is such that the number of die per wafer is decreased significantly.
As another way to cope with a higher rate of attrition on larger integrated circuits, some manufacturers bin these components according to the number and location of faults tested during the wafer sort. As an example, FIG. 1A illustrates a portion of an integrated circuit 100 with four parallel circuit blocks 102, 104, 106, 108, such as memory controllers. These four circuit blocks 102, 104, 106, 108 all have a corresponding connection 110 (e.g. pins P1 to P4) to interface with circuitry (not shown) external to the integrated circuit 100. However, a fault occurring on the second circuit block 104 has been found during wafer sort, so only connections 110 labeled P1, P3, and P4 can be subsequently used. The connection 110 to the second circuit block 104 is labeled as a no connect (NC) in FIG. 1A to indicate that external circuitry should not be connected to it. Components with the same interface combination as tested during wafer sort may be binned together and sold to a particular customer.
Even though only a single fault has occurred, a fault on a different circuit block may require an entirely different interface for external circuitry. For example, FIG. 1B depicts a single fault on the third circuit block 106 for the same portion of the integrated circuit 100. With this failure, only connections 110 labeled P1, P2, and P4 should be used, and the connection 110 to the third circuit block 106 is labeled as an NC. Even though these two integrated circuits 100 of FIGS. 1A-B have the same performance with the same number of functional circuit blocks and possess only a single fault, they cannot be exchanged for one another on a circuit board having traces to external circuitry interfacing with P1 through P4. The required interfaces are different between the two example integrated circuits 100. Thus, the integrated circuit 100 of FIG. 1B has to be sorted into a different bin than that of FIG. 1A's integrated circuit 100. Such binning adds manufacturing costs and customer logistic complexity, whether redundant circuits are used or not.
Accordingly, what is needed are improved circuits, methods, and apparatus for utilizing redundant circuitry on integrated circuits to increase manufacturing yields, preferably all without drastically increasing die area and circuit complexity.